1. Field of the Invention
The present invention relates to a multiprocessor gateway for multiple serial buses that transfer data in packet fashion.
2. Description of Related Art
The networking of control units, sensor apparatus, and actuators with the aid of a network or communication system made up of a communication connection, in particular a bus, and corresponding communication modules, has drastically increased in recent years in the design of modern motor vehicles or also in mechanical engineering, especially in the machine-tool sector and in automation. Synergistic effects resulting from the distribution of functions to multiple users, in particular control units, can be achieved in this context. The term used is “distributed systems.” Such distributed systems or networks are thus made up of the users and the bus system or multiple bus systems connecting those users. Communication between different stations or users is thus taking place more and more via a communication system, bus system, or network of this kind, over which the data to be transferred are transmitted in messages. This communication traffic on the bus system, access and receiving mechanisms, and error handling are regulated by a corresponding protocol, the name of the respective protocol often being used (as it also is here) as a synonym for the network or bus system itself.
In the automotive sector, for example, the controller area network (CAN) bus has become established as a protocol. This is an event-controlled protocol, i.e. protocol activities such as the sending of a message are initiated by events that originate outside the communication system. Unique access to the communication system or bus system is resolved by priority-based bit arbitration. A prerequisite for this is that a priority be assigned to the data being transferred, and thus to each message. The CAN protocol is very flexible, and it is thus easy to insert further users and messages as long as free priorities (message identifiers) still exist. The totality of all the messages to be sent in the network, with priorities and with their transmitting and receiving users and the corresponding communication modules, are stored in a list called the communication matrix.
An alternative approach to event-controlled, spontaneous communication is the exclusively time-controlled approach. All communication activities on the bus are strictly periodic. Protocol activities such as the sending of a message are triggered only by the passage of a time that applies to the bus system. Access to this medium is based on the apportioning of time regions in which a transmitter has an exclusive transmission right. As a rule, the message sequence must already be defined before initial startup. A schedule is therefore drawn up that meets the messages' requirements in terms of repetition rate, redundancy, deadlines, etc. This is called a “bus schedule.” One such bus system is, for example, TTP/C.
The advantages of both aforesaid bus types are combined in the time-controlled CAN approach, called TTCAN (time-triggered controller area network). This meets the requirements outlined above for time-controlled communication, and the requirements for a certain degree of flexibility. TTCAN achieves this by constructing the communication round in “exclusive” time windows for periodic messages of specific communication users, and in “arbitrating” time windows for spontaneous messages of multiple communication users. TTCAN is based substantially on a time-controlled, periodic communication that is timed, with the aid of a time-reference message, by a user or communication module (called the “time master”) that defines the principal time.
A further possibility for combining different transfer types is offered by the FlexRay protocol, which describes a fast, deterministic, and fault-tolerant bus system for use in particular in a motor vehicle. This protocol operates with the time division multiple access (TDMA) method, in which the users and the messages to be transferred are allocated fixed time slots in which they have exclusive access to the communication connection (the bus). The time slots repeat in a defined cycle, so that the point in time at which a message is transferred via the bus can be predicted exactly, and bus access occurs deterministically. For optimum utilization of the bandwidth for message transfer on the bus system, the cycle is subdivided into a static and a dynamic part. The fixed time slots are located in the static part at the beginning of a bus cycle. In the dynamic part, the time slots are assigned dynamically, and exclusive bus access therein is enabled for only a short time in each case. If no access occurs, access is authorized for the next user. This time span is referred to as a “mini-slot,” in which the system waits for access by the first user.
As just presented, a plurality of different transfer technologies, and therefore types of bus systems or networks, exist. It is often the case that multiple bus systems of the same or different types must be connected to one another. This purpose is served by a bus interface unit, called a “gateway.” A gateway is therefore an interface between different buses, which can be of the same or different types: the gateway forwards messages from one bus to one or more other buses. Known gateways are made up of multiple independent communication modules; the exchange of messages occurs via the processor interface (CPU interface) of the respective user or the corresponding interface module of the respective communication module. This CPU interface is heavily loaded by this data exchange in addition to the messages to be transferred to the user itself; in combination with the transfer structure resulting therefrom, this results in a relatively low data transfer speed. Integrated communication controllers or communication modules, which share a common message memory (also called message RAM) in order thereby to compensate for structural disadvantages, also exist. Integrated communication modules of this kind are, however, therefore very inflexible in terms of data transfer, and in particular are defined for a specific number of bus connections and usually also for the same bus system.
FIG. 1 shows a bus system according to the existing art. The bus system contains multiple communication modules or communication controllers (CC), to which serial data buses can be connected. The multiprocessor gateway depicted in FIG. 1 contains an internal system bus or peripheral bus to which, in addition to the communication modules, a host CPU and a so-called gateway unit, which represents a second processor, are connected. Communication within the multiprocessor gateway occurs in accordance with the master/slave principle: the communication modules operate as slave units, and the host CPU and the gateway unit function as master units. The communication modules, constituting slave units, do not themselves initiate a data transfer, but do so only when prompted by a master.
The host CPU configures, monitors, and controls the individual communication modules CC. The CPU reads received messages, processes them, and generates new messages. The CPU also handles the delivery of messages. In a simple gateway situation, for example, it is often necessary merely to read out the data received from a communication module and write it into one or more other communication modules for delivery. If a DMA controller is not used, the host CPU transfers the data in word-based fashion from the communication module into the data memory RAM or into a CPU-internal memory. The data are then processed and transferred into corresponding communication modules. The data memory RAM contains not only the data but also a program code that is executed by the CPU. In the data memory RAM the data are stored, for example, in the form of message objects or messages of communication modules CC for further processing by the CPU.
Communication modules CC represent the data connection from the multiprocessor gateway to the individual bus systems, i.e. to the serial buses. In a conventional multiprocessor gateway, the communication modules each have a message memory. The messages that are received and are to be delivered via the bus are deposited in the message memory. The host CPU can access the message memory, and the data objects contained therein, via a passive interface.
The peripheral bus or system bus serves to connect the individual components with one another. Under the control of the bus master, data are written into, and read out from, modules. The gateway unit handles control of the gateway functions. The gateway unit can be constituted, for example, by a coprocessor that controls internal message transfer. The gateway serves to relieve the load on the host CPU. The gateway functions taken on by the gateway unit encompass, for example, message processing, comparison and combination of new messages, and message delivery. These functions are performed by the gateway unit as bus master. The transfer bandwidth of the system bus is divided between the two master units, i.e. between the gateway unit and the bus master.
Depending on the complexity and number of masters, hierarchical bus systems can also be used in the peripheral bus or system bus.
FIG. 2 shows, by way of example, a hierarchical bus system having two hierarchical levels (Crossbar Interconnection Switches). The hierarchical structure of the bus system in the multiprocessor gateway depicted in FIG. 2 allows multiple internal data transfers to be performed simultaneously, provided the data transfer does not take place between the two hierarchical planes. In the example depicted in FIG. 2, one data transfer is occurring in hierarchical plane 1 between the CPU and the peripheral module, and a second data transfer is occurring between two communication modules on another hierarchical plane.
In conventional multiprocessor gateways, the data transfer bandwidth of the system bus or of a hierarchically structured bus system is divided between the bus masters. Different access methods are used in this context. For example, the same transfer bandwidth is allocated to each of the various bus masters. Alternatively, different master units can be allocated different priorities, and the master unit having the higher priority, e.g. the host CPU, takes precedence for data transfer.
Conventional multiprocessor gateways therefore have the disadvantage that a master unit must constantly wait until an internal data transfer can be executed. Access conflicts occur when different masters want to access the common system bus simultaneously. This increases latency times or waiting times for internal data transfer. For example, if the gateway unit is using the system bus for a data transfer, the host CPU itself experiences wait cycles until it can once again access data in a peripheral module or a communication module, or other memories. While a master's data transfer is in progress, another master unit therefore cannot access peripheral modules. During this waiting time, the host CPU also cannot perform any data processing operations.